The present disclosure relates generally to semiconductor processing, and more particularly to a method for smart dummy insertion that optimizes the number of dummy insertions while preserving a chemical mechanical polishing (CMP) quality.
A dual damascene process is generally adopted in semiconductor fabrication when feature size is scaled down and technology moves to submicron. In the dual damascene process, copper is generally used as conductive material for interconnection. Other conductive materials include tungsten, titanium, titanium nitride. Accordingly, silicon oxide, fluorinated silica glass, or low dielectric constant (k) materials are used for inter-level dielectric (ILD). A chemical mechanical polishing (CMP) technique is used to etch back and globally planarize the conductive material and/or ILD at a wafer surface. CMP involves both mechanical grinding and chemical etching in the material removal process.
However, because the removal rate of metal and dielectric materials are usually different, polishing selectivity leads to undesirable dishing and erosion effects. Dishing often occurs when the metal recedes below or protrudes above the level of the adjacent dielectric. Erosion is a localized thinning of the dielectric. Dishing and erosion are sensitive to pattern structure and pattern density. Therefore, dummy metal features are designed and incorporated into the damascene structure to make pattern density more uniform and to improve the planarization process.
Other processes using CMP also suffer from similar problems. For example, shallow trench isolation (STI) uses CMP to form a global planarized profile. Over-etching is typically performed to ensure a complete etch of the silicon oxide on silicon nitride. Surface variations associated with local pattern and pattern density may be eliminated by the use of dummy features such as dummy active features in STI trench.
Generally, dummy insertion methods are based on local density rules that add dummy features universally across the wafer to achieve a target uniform density. By doing this, excess dummy features may be formed, thereby increasing the time and costs of semiconductor fabrication. As new process technologies emerge and circuit designs become increasingly complex, these problems will be magnified. Furthermore, these unnecessary dummy features may degrade device performance such as increasing parasitic capacitance. What is needed is a simple and cost-effective method for optimizing the number of dummy features while preserving CMP quality.